The present invention generally relates to an improved synchronizing circuit and particularly to a synchronizing circuit of the type which provides a synchronizing signal having a first level during a fractional portion of each synchronizing signal period and a second level during the remaining fractional portion of each synchronizing period. The present invention is more particularly directed to such a synchronizing circuit which includes means for maintaining the synchronizing signal periods and the respective fractional portions thereof constant.
There are many applications in modern electronic technology wherein a synchronizing signal is required. One such application is in the field of data transmission wherein a timing pulse is required followed by a period for data transmission. For example, such a synchronizing signal may be at a high level for one-fourth of the synchronizing signal period for synchronization and at a low level for three-fourths of the synchronizing signal periods during which time date is transmitted.
Such a synchronizing signal is generally generated by a synchronizing circuit which responds to a first clock signal having a relatively low frequency (f.sub.1) and a second clock signal having a relatively high frequency (f.sub.2) equal to, for example, four times the first clock signal frequency. Such circuits utilize the first clock signal to control the duration of a timing period and the second clock signal to derive, through counting means, the high and low outputs for the proper time durations. In the above example, the second clock signal would be used to derive a high output for two half-cycles of the second clock signal and a low output for six half-cycles of the second clock signal. Other duty cycles are also obtainable depending upon the number of counting means stages and the number of multiples of the second clock signal frequency as compared to the first clock signal frequency.
While such synchronizing circuits have been generally successful in the past, there is a problem which can arise during their operation under certain conditions when the relative frequencies of the first and second clock signals are not exact multiples of each other and when there is a phase difference between the first and second clock signals. In some cases, under such conditions, the relative frequencies and phase relationships of the first and second clock signals can result in the synchronizing circuit not providing the properly timed synchronizing signal. More specifically, under such conditions, the synchronizing circuits may provide a synchronizing signal wherein the synchronizing signal period is not constant and therefore, the ratio of the high and low level periods can correspondingly change. This results because the counting means does not always count the same number of second clock signal half-cycles for each counting period. During some counting periods, the counting means may count for all eight half-cycles of the second clock signal and during other counting periods, the counting means may count for only six half-cycles of the second clock signal. The result is a synchronizing signal which may have a high to low level ratio of 1:2 for some counting periods and a high to low ration of 1:3 for other counting periods.
The present invention overcomes these problems by providing, in addition to the counting means, an inhibit means to preclude the timing means from beginning a new counting period until after it has counted the required number of half-cycles of the second clock signal. This assures that the synchronizing signal periods and the ratio of the high to low level portions of the synchronizing signal periods remain constant.
The inhibit means of the circuit allows a given cycle of the first clock signal to vary to as low as n-1/2 complete cycles of the second clock signal while continuing to guarantee the synchronized signal output response described above provided that the variation is compensated for in the subsequent cycles of the first clock signal.